SystemC Totally Explained

Everything about Systemc totally explained

SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling and behavioral modeling. SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by ordinary C++ syntax. Instantiated in the SystemC framework, the objects described in this manner may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. The behaviours (processes) defined may be instantiated any number of times, and provisions are made for processes defined by hierarchies of other processes, as one would expect.
The language thus offered has semantical similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these. On the other hand, greater freedom of expressiveness is offered in return, like object oriented design partitioning and template classes. Which is more: SystemC is both a description language and a simulation kernel. The code written will compile together with the library's simulation kernel to give an executable that behaves like the described model when it's run. The performance of this simulation kernel isn't to be compared with that of commercial VHDL/Verilog simulators designed to simulate RTL level designs at the present.

History

1999/09/27 Open SystemC Initiative announced
2000/03/01 SystemC V0.91 released
2000/03/28 SystemC V1.0 released
2001/02/01 SystemC V2.0 specification and V1.2 Beta source code released
2003/06/03 SystemC 2.0.1 LRM (language reference manual) released
2005/06/06 SystemC 2.1 LRM and TLM 1.0 transaction-level modeling standard released
2005/12/12 IEEE approves the IEEE 1666–2005 standard for SystemC
2007/04/13 SystemC v2.2 released

SystemC was originally developed by Synopsys, Inc., an Electronic Design Automation (EDA) company, to act as the modeling foundation for forthcoming system simulation and synthesis tools. A number of Synopsys' end-users suggested that the only way a modeling environment like SystemC would be adopted broadly, would be as an open source project. Synopsys teamed with a number of large electronics companies, ARM Ltd. and CoWare to launch SystemC in 1999. The chief competitor at the time was another C++ based open source package offered by a small startup called CynApps which later became Forte Design Automation. In June 2000, a standards group known as the Open SystemC Initiative was formed to provide an industry neutral organization to host SystemC activities and to allow Synopsys' largest competitors, Cadence and Mentor Graphics, democratic representation in SystemC development.

Language Features

Modules

Modules are the basic building blocks of a SystemC design hierarchy. A SystemC model usually consists of several modules which communicate via ports.

Ports

Ports allow communication from inside a module to the outside (usually to other modules)

Processes

Processes are the main computation elements. They are concurrent.

Channels

Channels are the communication elements of SystemC. They can be either simple wires or complex communication mechanisms like fifos or bus channels. Elementary Channels:

signal

buffer

fifo

mutex

semaphore

Interfaces

Ports use interfaces to communicate with channels.

Events

Allow the synchronization between processes.

Data types

SystemC introduces several data types which support the modeling of hardware. Extended standard types:

sc_int<> 64-bit signed integer

sc_uint<> 64-bit unsigned integer

sc_bigint<> arbitrary precision signed integer

sc_biguint<> arbitrary precision unsigned integer Logic types:

sc_bit 2-valued single bit

sc_logic 4-valued single bit

sc_bv<> vector of sc_bit

sc_lv<> vector of sc_logic Fixed point types:

sc_fixed<> templated signed fixed point

sc_ufixed<> templated unsigned fixed point

sc_fix untemplated signed fixed point

sc_ufix untemplated unsigned fixed point

Example

Example code of an adder:

 include "systemc.h"

SC_MODULE(adder)          // module (class) declaration
;

Further Information

Get more info on 'Systemc'.

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